Hardware designers continue to move memory closer and closer to the processor cores within computer systems. Now, dynamic random access memory is being included within the same packages, also known as semiconductor integrated circuit packages, as processors. This memory is referred to as embedded dynamic random access memory (eDRAM). Embedding DRAM on the same package as processing units allows designers to achieve higher speeds with lower latency. As such, eDRAM is a performance augmenter for multi-core and/or graphics processors. Serving as write-back cache, eDRAM improves premium integrated graphics performance and is effective in caching high-bandwidth multi-core traffic. However, eDRAM may not increase performance for other workloads.
Just as with other DRAM, an active eDRAM requires periodic refreshing of the capacitors that comprise the DRAM memory arrays as those capacitors leak charge. Thus, there is a level of power consumption associated with eDRAM even when the eDRAM is not being actively accessed. For example with different bandwidth of accesses and self-refresh, some eDRAM has been seen to consume 5 W of power while at other times, eDRAM has been seen to consume 68 W of power.
Furthermore, power management is becoming more challenging than ever before in all segments of computer-based systems. Optimizing systems for maximum or required performance at the minimum power consumption is usually done as a combination of software (operating system) and hardware elements. Most modern operating systems use the Advanced Configuration and Power Interface (“ACPI”) standard. The ACPI processor sleep state control assumes that the core can be in different power-saving states (also termed sleep states or C-states) marked as C0 to Cn. However, there are currently no mechanisms for power management of eDRAM regardless of the operational state of the eDRAM or the processor cores. The processor cores can be general purpose such as central processors, or special purpose such as graphics engines or signal processors.